Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version3064766
date_generatedFri Jun 11 10:31:02 2021 os_platformWIN64
product_versionVivado v2020.2 (64-bit) project_id22c5f3c8c075412aac73dcf03efbe4e7
project_iteration214 random_id4a563824606552e4a83491e92929bc30
registration_id211376274_0_0_851 route_designTRUE
target_devicexc7z010i target_familyzynq
target_packageclg400 target_speed-1L
tool_flowVivado

user_environment
cpu_nameAMD Ryzen 9 3900X 12-Core Processor cpu_speed3793 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram17.000 GB total_processors2

vivado_usage
gui_handlers
abstractsearchablepanel_show_search=1 addsrcwizard_specify_hdl_netlist_block_design=2 addsrcwizard_specify_or_create_constraint_files=1 archiveprojectdialog_archive_name=5
basedialog_apply=4 basedialog_cancel=303 basedialog_no=5 basedialog_ok=129
basedialog_yes=205 cmdmsgdialog_messages=4 cmdmsgdialog_ok=48 cmdmsgdialog_open_messages_view=7
commandsinput_type_tcl_command_here=8 confirmsavetexteditsdialog_no=3 constraintschooserpanel_add_files=1 constraintschooserpanel_file_table=1
copyiphandler_destination_ip_name=2 coretreetablepanel_core_tree_table=18 customizecoredialog_documentation=3 customizecoredialog_ip_location=1
designtimingsumsectionpanel_worst_negative_slack=1 expruntreepanel_exp_run_tree_table=3 filesetpanel_file_set_panel_tree=826 floatingtopdialog_select_top_module_of_your_design=1
floatingtopdialog_specify_new_top_module=1 flownavigatortreepanel_flow_navigator_tree=741 gettingstartedview_create_new_project=1 gettingstartedview_open_example_project=1
hardwaretreepanel_hardware_tree_table=556 hardwareview_expand_next_level=1 hcodeeditor_search_text_combo_box=141 heditorpane_copy=1
hpopuptitle_close=3 ipcoreview_tabbed_pane=2 ipstatussectionpanel_ip_up_to_date=4 ipstatussectionpanel_upgrade_selected=12
ipstatustablepanel_ip_status_table=47 ipstatustablepanel_more_info=1 languagetemplatesdialog_templates_tree=53 launchpanel_dont_show_this_dialog_again=1
launchpanel_generate_scripts_only=1 launchpanel_launch_runs_on_local_host=1 logmonitor_monitor=1 mainmenumgr_checkpoint=33
mainmenumgr_constraints=1 mainmenumgr_edit=98 mainmenumgr_export=8 mainmenumgr_file=158
mainmenumgr_flow=79 mainmenumgr_help=2 mainmenumgr_import=9 mainmenumgr_io_planning=1
mainmenumgr_ip=24 mainmenumgr_open_recent_project=45 mainmenumgr_project=74 mainmenumgr_reports=76
mainmenumgr_settings=5 mainmenumgr_text_editor=16 mainmenumgr_timing=1 mainmenumgr_tools=99
mainmenumgr_view=16 mainmenumgr_window=90 maintoolbarmgr_run=1 mainwinmenumgr_layout=49
mainwintoolbarmgr_select_or_save_window_layout=3 messagewithoptiondialog_dont_show_this_dialog_again=4 msgtreepanel_message_view_tree=562 msgview_clear_messages_resulting_from_user_executed=22
msgview_critical_warnings=15 msgview_error_messages=5 msgview_information_messages=9 msgview_warning_messages=36
navigabletimingreporttab_timing_report_navigation_tree=28 netlisttreeview_netlist_tree=5 newhardwaredashboarddialog_name=2 numjobschooser_number_of_jobs=1
openfileaction_cancel=1 pacommandnames_add_sources=23 pacommandnames_archive_project=5 pacommandnames_auto_connect_target=67
pacommandnames_auto_update_hier=50 pacommandnames_bitstream_settings=5 pacommandnames_close_hardware_design=1 pacommandnames_close_project=2
pacommandnames_copy_ip=2 pacommandnames_core_gen=1 pacommandnames_create_hardware_dashboards=3 pacommandnames_create_svf_target=1
pacommandnames_design_ahead_synth=1 pacommandnames_fileset_window=8 pacommandnames_generate_composite_file=1 pacommandnames_hardware_window=2
pacommandnames_ip_packager_wizard=2 pacommandnames_language_templates=1 pacommandnames_message_window=1 pacommandnames_open_checkpoint=1
pacommandnames_open_project=4 pacommandnames_open_target_wizard=1 pacommandnames_packager_create_interface_definition=1 pacommandnames_program_fpga=313
pacommandnames_project_summary=7 pacommandnames_recustomize_core=1 pacommandnames_refresh_device=2 pacommandnames_refresh_server=2
pacommandnames_report_ip_status=1 pacommandnames_reports_window=2 pacommandnames_run_bitgen=53 pacommandnames_run_implementation=1
pacommandnames_save_project_as=1 pacommandnames_set_as_top=6 pacommandnames_show_product_guide=1 pacommandnames_simulation_run=8
pacommandnames_synth_settings=2 pacommandnames_tcl_console_window=1 pacommandnames_verify_device=2 pacommandnames_write_checkpoint=1
pacommandnames_write_config_memory_file=1 pathreporttableview_description=2 paviews_code=132 paviews_device=4
paviews_path_table=2 paviews_project_summary=23 programfpgadialog_program=302 programfpgadialog_specify_bitstream_file=22
progressdialog_background=3 progressdialog_cancel=22 projectnamechooser_project_name=1 projectsummarydrcpanel_open_drc_report=2
projectsummarytimingpanel_open_timing_summary_report=2 projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=1 propertiesview_automatically_update=2 rdicommands_copy=1
rdicommands_custom_commands=18 rdicommands_delete=15 rdicommands_properties=6 rdicommands_settings=2
rdicommands_undo=1 reportipstatusinfodialog_report_ip_status=1 reporttimingsummarydialog_report_timing_summary_dialog_tabbed=5 rungadget_show_error=1
rungadget_show_error_and_critical_warning_messages=8 rungadget_show_warning_and_error_messages_in_messages=4 saveprojectutils_dont_save=1 saveprojectutils_save=6
selecttopmoduledialog_select_top_module=6 settingsdialog_project_tree=9 settingsdialog_restore=1 simpleoutputproductdialog_close_dialog_unsaved_changes_will=1
simpleoutputproductdialog_generate_output_products_immediately=8 simpleoutputproductdialog_output_product_tree=6 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=28 srcchooserpanel_create_file=1
srcchoosertable_src_chooser_table=7 srcmenu_ip_documentation=10 srcmenu_ip_hierarchy=34 stalerundialog_no=1
stalerundialog_open_design=1 stalerundialog_yes=6 statemonitor_reset_run=15 statemonitor_reset_step=1
syntheticagettingstartedview_recent_projects=6 syntheticastatemonitor_cancel=52 taskbanner_close=1 tclconsoleview_copy=1
tclconsoleview_tcl_console_code_editor=5 tclobjecttreetable_treetable=9 tclobjectview_sort_properties=1 timinggettingstartedpanel_check_timing=1
timinggettingstartedpanel_report_timing=1 timinggettingstartedpanel_report_timing_summary=1 timingitemflattablepanel_table=27 timingsumresultstab_show_only_failing_checks=1
touchpointsurveydialog_no=2 verifydevicedialog_specify_bitstream_file=1 viotreetablepanel_vio_tree_table=8 xpg_ipsymbol_show_disabled_ports=1
java_command_handlers
addsources=25 archiveproject=5 autoconnecttarget=64 closedesign=1
closeproject=2 copyiphandler=2 coreview=1 createblockdesign=1
createhardwaredashboards=3 createinterfacedefinitionhandler=1 createsvftarget=1 editcopy=1
editdelete=72 editpaste=33 editproperties=6 editundo=6
exitapp=20 ippackagerwizardhandler=2 launchopentarget=2 launchprogramfpga=315
managecompositetargets=1 newhardwaredashboard=12 newproject=1 opencheckpoint=1
openexistingreport=4 openhardwaremanager=27 openproject=5 openrecenttarget=13
projectsummary=7 recustomizecore=23 refreshdevice=2 refreshserver=2
reportipstatus=2 reporttimingsummary=6 runbitgen=503 rundesignahead=1
runimplementation=36 runsynthesis=6 savefileproxyhandler=27 saveprojectas=1
settopnode=6 showproductguide=1 showview=88 toolssettings=10
toolstemplates=1 upgradeip=5 verifydevice=2 viewlayoutcmd=3
viewtaskimplementation=11 viewtasksynthesis=1 writecheckpoint=1
other_data
guimode=22
project_data
constraintsetcount=1 core_container=true currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=40 export_simulation_ies=40
export_simulation_modelsim=40 export_simulation_questa=40 export_simulation_riviera=40 export_simulation_vcs=40
export_simulation_xsim=40 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=23 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=6 totalsynthesisruns=7

unisim_transformation
post_unisim_transformation
bufg=7 bufio=1 bufr=2 carry4=54
fdce=102 fdre=461 fdse=16 gnd=21
ibuf=28 lut1=39 lut2=92 lut3=102
lut4=216 lut5=150 lut6=319 mmcme2_adv=1
muxf7=24 obuf=31 obufds=4 oserdese2=7
plle2_adv=1 ramb36e1=60 vcc=20
pre_unisim_transformation
bufg=7 bufio=1 bufr=2 carry4=54
fdce=102 fdre=461 fdse=16 gnd=21
ibuf=28 lut1=39 lut2=92 lut3=102
lut4=216 lut5=150 lut6=319 mmcme2_adv=1
muxf7=24 obuf=31 obufds=4 oserdese2=7
plle2_adv=1 ramb36e1=60 vcc=20

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=54 bram_ports_newly_gated=30 bram_ports_total=120 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=579 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
clk_wiz_v6_0_6_0_0/1
clkin1_period=37.037 clkin2_period=10.0 clock_mgr_type=NA component_name=clk27m25p2m
core_container=NA enable_axi=0 feedback_source=FDBK_ONCHIP feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=5 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
clk_wiz_v6_0_6_0_0/2
clkin1_period=8.000 clkin2_period=10.000 clock_mgr_type=NA component_name=pll125m27m
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=true use_phase_alignment=true
use_power_down=false use_reset=true
selectio_wiz_v5_1_15/1
active_edge=RISING bus_dir=OUTPUTS bus_in_delay=NONE bus_io_std=TMDS_33
bus_out_delay=NONE bus_sig_type=DIFF clk_buf=BUFIO2 clk_delay=NONE
clk_io_std=LVCMOS18 clk_sig_type=SINGLE component_name=TMDS_TX core_container=true
ddr_alignment=C0 enable_bitslip=false enable_train=false interface_type=NETWORKING
iptotal=1 selio_active_edge=DDR selio_bus_in_delay=NONE selio_bus_in_tap=0
selio_bus_out_delay=NONE selio_bus_out_tap=0 selio_clk_buf=MMCM selio_clk_io_std=TMDS_33
selio_clk_sig_type=DIFF selio_ddr_alignment=SAME_EDGE_PIPELINED selio_interface_type=NETWORKING selio_oddr_alignment=SAME_EDGE
serialization_factor=10 system_data_width=3 use_phase_detector=false use_serialization=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
reqp-1577=1 zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
ckbf-1=1 timing-14=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.000112 clocks=0.001730
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.084060 die=xc7z010iclg400-1L dsp_output_toggle=12.500000 dynamic=0.352190
effective_thetaja=11.53 enable_probability=0.990000 family=zynq ff_toggle=12.500000
flow_state=routed heatsink=none i/o=0.131526 input_toggle=12.500000
junction_temp=30.0 (C) logic=0.000812 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 mmcm=0.092397 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.436251 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=clg400 pct_clock_constrained=2.000000 pct_inputs_defined=3
platform=nt64 pll=0.124909 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.000705 simulation_file=None speedgrade=-1L static_prob=False
temp_grade=industrial thetajb=9.3 (C/W) thetasa=0.0 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=11.53 user_junc_temp=30.0 (C) user_thetajb=9.3 (C/W)
user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.018000 vccadc_total_current=0.018000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.114565 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.005268 vccaux_total_current=0.119833
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000011 vccbram_static_current=0.001297 vccbram_total_current=0.001308
vccbram_voltage=0.950000 vccint_dynamic_current=0.015731 vccint_static_current=0.003215 vccint_total_current=0.018946
vccint_voltage=0.950000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.039703 vcco33_static_current=0.001000 vcco33_total_current=0.040703
vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000 vcco_ddr_total_current=0.000000
vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000
vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000
vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.009297 vccpaux_total_current=0.009297
vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.012997 vccpint_total_current=0.012997
vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.002700 vccpll_total_current=0.002700
vccpll_voltage=1.800000 version=2020.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=4 bufgctrl_util_percentage=12.50
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=8 bufio_fixed=0 bufio_only_fixed=0 bufio_only_used=1
bufio_used=1 bufio_util_percentage=12.50 bufmrce_available=4 bufmrce_fixed=0
bufmrce_used=0 bufmrce_util_percentage=0.00 bufr_available=8 bufr_fixed=0
bufr_used=2 bufr_util_percentage=25.00 mmcme2_adv_available=2 mmcme2_adv_fixed=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=50.00 plle2_adv_available=2 plle2_adv_fixed=0
plle2_adv_used=1 plle2_adv_util_percentage=50.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=60 block_ram_tile_fixed=0 block_ram_tile_used=60 block_ram_tile_util_percentage=100.00
ramb18_available=120 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=60 ramb36_fifo_fixed=0 ramb36_fifo_used=60 ramb36_fifo_util_percentage=100.00
ramb36e1_only_used=60
primitives
bufg_functional_category=Clock bufg_used=4 bufio_functional_category=Clock bufio_used=1
bufr_functional_category=Clock bufr_used=2 carry4_functional_category=CarryLogic carry4_used=54
fdce_functional_category=Flop & Latch fdce_used=107 fdre_functional_category=Flop & Latch fdre_used=461
fdse_functional_category=Flop & Latch fdse_used=16 ibuf_functional_category=IO ibuf_used=28
lut1_functional_category=LUT lut1_used=34 lut2_functional_category=LUT lut2_used=92
lut3_functional_category=LUT lut3_used=126 lut4_functional_category=LUT lut4_used=216
lut5_functional_category=LUT lut5_used=150 lut6_functional_category=LUT lut6_used=349
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=24
obuf_functional_category=IO obuf_used=31 obufds_functional_category=IO obufds_used=4
oserdese2_functional_category=IO oserdese2_used=7 plle2_adv_functional_category=Clock plle2_adv_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=60
slice_logic
f7_muxes_available=8800 f7_muxes_fixed=0 f7_muxes_used=24 f7_muxes_util_percentage=0.27
f8_muxes_available=4400 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=17600 lut_as_logic_fixed=0 lut_as_logic_used=798 lut_as_logic_util_percentage=4.53
lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=584 register_as_flip_flop_util_percentage=1.66
register_as_latch_available=35200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=17600 slice_luts_fixed=0 slice_luts_used=798 slice_luts_util_percentage=4.53
slice_registers_available=35200 slice_registers_fixed=0 slice_registers_used=584 slice_registers_util_percentage=1.66
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=17600 lut_as_logic_fixed=0
lut_as_logic_used=798 lut_as_logic_util_percentage=4.53 lut_as_memory_available=6000 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=91 lut_in_front_of_the_register_is_used_fixed=91 lut_in_front_of_the_register_is_used_used=42
register_driven_from_outside_the_slice_fixed=42 register_driven_from_outside_the_slice_used=133 register_driven_from_within_the_slice_fixed=133 register_driven_from_within_the_slice_used=451
slice_available=4400 slice_fixed=0 slice_registers_available=35200 slice_registers_fixed=0
slice_registers_used=584 slice_registers_util_percentage=1.66 slice_used=349 slice_util_percentage=7.93
slicel_fixed=0 slicel_used=216 slicem_fixed=0 slicem_used=133
unique_control_sets_available=4400 unique_control_sets_fixed=4400 unique_control_sets_used=23 unique_control_sets_util_percentage=0.52
using_o5_and_o6_fixed=0.52 using_o5_and_o6_used=169 using_o5_output_only_fixed=169 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=629
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified] -max_bram=default::-1
-max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1
-mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7z010iclg400-1L -resource_sharing=default::auto
-retiming=[specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified]
-seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3 -top=cq_pmod_upscan
-verilog_define=default::[not_specified]
usage
elapsed=00:00:36s hls_ip=0 memory_gain=57.207MB memory_peak=1056.742MB