Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version3064766
date_generatedFri Jun 11 10:27:25 2021 os_platformWIN64
product_versionVivado v2020.2 (64-bit) project_id8d3c50102f7e4ce9931f8af7896e9929
project_iteration376 random_id4a563824606552e4a83491e92929bc30
registration_id211376274_0_0_851 route_designTRUE
target_devicexc7s50 target_familyspartan7
target_packagecsga324 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD Ryzen 9 3900X 12-Core Processor cpu_speed3793 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram17.000 GB total_processors2

vivado_usage
gui_handlers
abstractsearchablepanel_show_search=1 addsrcwizard_specify_hdl_netlist_block_design=3 addsrcwizard_specify_or_create_constraint_files=2 addsrcwizard_specify_simulation_specific_hdl_files=1
archiveprojectdialog_archive_name=1 basedialog_apply=11 basedialog_cancel=396 basedialog_no=8
basedialog_ok=208 basedialog_yes=220 closeplanner_cancel=1 cmdmsgdialog_messages=6
cmdmsgdialog_ok=97 cmdmsgdialog_open_messages_view=7 cmdmsgtreedialog_ok=7 commandsinput_type_tcl_command_here=13
commonoptionschooserpanel_specify_generics_parameters=1 configruntablepanel_config_run_table=3 confirmsavetexteditsdialog_no=6 constraintschooserpanel_add_files=1
copyiphandler_destination_ip_name=7 coretreetablepanel_core_tree_table=171 customizecoredialog_documentation=7 customizecoredialog_ip_location=3
customizecoredialog_switch_to_defaults=2 designtimingsumsectionpanel_worst_negative_slack=1 deviceview_show_cell_connections=3 editcreateclocktablepanel_edit_create_clock_table=2
editcreategeneratedclocktablepanel_edit_create_generated_clock_table=10 expruntreepanel_exp_run_tree_table=3 filesetpanel_disable_core_container=1 filesetpanel_file_set_panel_tree=1335
floatingtopdialog_select_top_module_of_your_design=1 floatingtopdialog_specify_new_top_module=1 flownavigatortreepanel_flow_navigator_tree=1048 flownavigatortreepanel_reset_synthesis_run=1
fpgachooser_fpga_table=5 generatedclockcreationpanel_clock_name=2 generatedclockcreationpanel_optional_divide_frequency=1 getobjectsdialog_find=20
getobjectspanel_set=2 gettingstartedview_open_example_project=1 graphicalview_select=1 graphicalview_zoom_in=39
graphicalview_zoom_out=132 hardwaredeviceproppanels_specify_bitstream_file=2 hardwaredeviceproppanels_specify_probes_file=1 hardwaretreepanel_hardware_tree_table=872
hcodeeditor_search_text_combo_box=178 hduallist_find_results=23 heditorpane_copy=1 hjfilechooserrecentlistpreview_recent_directories=1
hpopuptitle_close=3 incrementalrunpanel_turn_incremental_implementation_on=1 instancemenu_floorplanning=76 ipstatussectionpanel_ip_up_to_date=4
ipstatussectionpanel_re_run_report=1 ipstatussectionpanel_upgrade_selected=13 ipstatustablepanel_ip_status_table=47 ipstatustablepanel_more_info=1
labtoolsmenu_jtag_scan_rate=1 languageoptionspanel_loop_count=2 languagetemplatesdialog_templates_tree=53 launchpanel_dont_show_this_dialog_again=1
launchpanel_generate_scripts_only=1 launchpanel_launch_runs_on_local_host=1 launchrunmsgdialog_cancel_run=1 logmonitor_monitor=4
mainmenumgr_checkpoint=61 mainmenumgr_constraints=1 mainmenumgr_edit=162 mainmenumgr_export=8
mainmenumgr_file=252 mainmenumgr_floorplanning=1 mainmenumgr_flow=138 mainmenumgr_help=4
mainmenumgr_import=7 mainmenumgr_io_planning=2 mainmenumgr_ip=42 mainmenumgr_open=3
mainmenumgr_open_recent_project=93 mainmenumgr_project=149 mainmenumgr_reports=126 mainmenumgr_settings=16
mainmenumgr_text_editor=15 mainmenumgr_timing=2 mainmenumgr_tools=135 mainmenumgr_view=20
mainmenumgr_window=157 maintoolbarmgr_run=9 mainwinmenumgr_layout=73 mainwintoolbarmgr_select_or_save_window_layout=3
messagewithoptiondialog_dont_show_this_dialog_again=5 modifiedconstraintswithouttargetdialog_update=2 msgtreepanel_message_view_tree=881 msgview_clear_messages_resulting_from_user_executed=35
msgview_critical_warnings=42 msgview_error_messages=12 msgview_information_messages=21 msgview_status_messages=6
msgview_warning_messages=75 navigabletimingreporttab_timing_report_navigation_tree=13 netlistschmenuandmouse_expand_collapse=2 netlisttreeview_floorplanning=5
netlisttreeview_netlist_tree=1363 newhardwaredashboarddialog_name=3 newprojectwizard_configure_example_design_create=2 newprojectwizard_imported_project_create_project=1
newprojectwizard_project_is_a_vitis_platform=1 newprojectwizard_specify_ise_file=1 numjobschooser_number_of_jobs=1 openfileaction_cancel=3
pacommandnames_add_config_memory=5 pacommandnames_add_sources=40 pacommandnames_archive_project=1 pacommandnames_auto_connect_target=93
pacommandnames_auto_update_hier=61 pacommandnames_bel_const_mode=2 pacommandnames_bitstream_settings=8 pacommandnames_close_hardware_design=1
pacommandnames_close_project=3 pacommandnames_copy_ip=7 pacommandnames_core_gen=3 pacommandnames_create_hardware_dashboards=4
pacommandnames_create_svf_target=1 pacommandnames_design_ahead_synth=3 pacommandnames_device_constraints_window=1 pacommandnames_device_view=3
pacommandnames_fileset_window=17 pacommandnames_generate_composite_file=1 pacommandnames_hardware_window=1 pacommandnames_highlight_default_color=7
pacommandnames_language_templates=1 pacommandnames_message_window=1 pacommandnames_netlist_window=1 pacommandnames_new_project=1
pacommandnames_open_project=6 pacommandnames_open_target_wizard=1 pacommandnames_program_fpga=535 pacommandnames_project_summary=9
pacommandnames_recustomize_core=7 pacommandnames_refresh_device=2 pacommandnames_refresh_server=2 pacommandnames_refresh_target=1
pacommandnames_reload_impl_design=1 pacommandnames_report_ip_status=2 pacommandnames_reports_window=2 pacommandnames_run_bitgen=263
pacommandnames_run_implementation=3 pacommandnames_run_synthesis=1 pacommandnames_save_project_as=1 pacommandnames_set_as_top=6
pacommandnames_show_product_guide=5 pacommandnames_simulation_close=1 pacommandnames_simulation_live_break=4 pacommandnames_simulation_live_restart=1
pacommandnames_simulation_live_run_all=9 pacommandnames_simulation_relaunch=2 pacommandnames_simulation_run=14 pacommandnames_simulation_run_behavioral=39
pacommandnames_simulation_settings=3 pacommandnames_src_disable=1 pacommandnames_src_replace_file=3 pacommandnames_synth_settings=4
pacommandnames_tcl_console_window=1 pacommandnames_unhighlight_selection=9 pacommandnames_unroute=1 pacommandnames_verify_device=4
pacommandnames_write_config_memory_file=1 pacommandnames_zoom_fit=1 pacommandnames_zoom_in=12 pacommandnames_zoom_out=14
pathreporttableview_description=2 paviews_code=216 paviews_dashboard=1 paviews_device=242
paviews_ip_catalog=1 paviews_path_table=1 paviews_project_summary=68 paviews_schematic=1
primitivesmenu_default=4 primitivesmenu_highlight_leaf_cells=57 primitivesmenu_select_leaf_cell_parents=1 primitivesmenu_select_leaf_cells=26
primitivesmenu_unhighlight_leaf_cells=4 programfpgadialog_program=523 programfpgadialog_specify_bitstream_file=28 progressdialog_background=3
progressdialog_cancel=29 projectnamechooser_project_name=2 projectsettingssimulationpanel_select_testbench_top_module=1 projectsettingssimulationpanel_tabbed_pane=10
projectsummarydrcpanel_open_drc_report=1 projectsummarytimingpanel_open_timing_summary_report=2 projectsummaryutilizationgadget_project_summary_utilization_gadget_tabbed=1 projecttab_reload=2
propertiesview_automatically_update=2 rdicommands_custom_commands=15 rdicommands_delete=13 rdicommands_properties=11
rdicommands_settings=2 rdiviews_waveform_viewer=144 removesourcesdialog_also_delete=2 reportipstatusinfodialog_report_ip_status=1
rungadget_show_error=1 rungadget_show_error_and_critical_warning_messages=8 rungadget_show_warning_and_error_messages_in_messages=4 saveprojectutils_dont_save=6
saveprojectutils_save=16 schematicview_remove=1 schmenuandmouse_expand_cone=2 sdcgetobjectspanel_specify_generated_clock_source_objects=2
sdcgetobjectspanel_specify_master_clock=8 sdcgetobjectspanel_specify_master_pin=5 selectmenu_highlight=57 selectmenu_mark=16
selecttopmoduledialog_select_top_module=7 settingsdialog_options_tree=35 settingsdialog_project_tree=64 settingsdialog_restore=2
settingsprojectgeneralpage_choose_device_for_your_project=1 settingsprojectippackagerpage_delete_project_after_packaging=2 settingsprojectippackagerpage_include_source_project_archive=2 settingsprojectippage_delete_ip_cache=2
settingsprojectippage_generate_log_file=2 settingsprojectippage_ip_synthesis_cache_location=1 simpleoutputproductdialog_close_dialog_unsaved_changes_will=1 simpleoutputproductdialog_generate_output_products_immediately=14
simpleoutputproductdialog_output_product_tree=6 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=44 srcchooserpanel_create_file=1 srcchoosertable_src_chooser_table=6
srcmenu_ip_documentation=23 srcmenu_ip_hierarchy=42 stalerundialog_no=1 stalerundialog_open_design=1
stalerundialog_yes=7 statemonitor_reset_run=20 statemonitor_reset_step=1 syntheticagettingstartedview_recent_projects=8
syntheticastatemonitor_cancel=83 taskbanner_close=1 tclconsoleview_clear_all_output_in_tcl_console=1 tclconsoleview_copy=1
tclconsoleview_tcl_console_code_editor=55 tclobjecttreetable_treetable=9 tclobjectview_sort_properties=1 timinggettingstartedpanel_check_timing=1
timinggettingstartedpanel_report_timing=1 timinggettingstartedpanel_report_timing_summary=1 timingitemflattablepanel_table=20 touchpointsurveydialog_no=2
verifydevicedialog_specify_bitstream_file=2 verifydevicedialog_verify=1 viotreetablepanel_vio_tree_table=1 waveformnametree_waveform_name_tree=9
waveformview_goto_time_0=10 waveformview_next_transition=1 waveformview_previous_transition=1 xdccategorytree_xdc_category_tree=14
xdceditorview_apply_all_changes_to_xdc_constraints=1 xdcviewertreetablepanel_xdc_viewer_tree_table=1 xpg_tabbedpane_tabbed_pane=5
java_command_handlers
addsources=43 archiveproject=1 autoconnecttarget=90 closedesign=1
closeproject=3 copyiphandler=7 coreview=3 createblockdesign=1
createhardwaredashboards=3 createsvftarget=1 customizecore=3 editcopy=1
editdelete=108 editpaste=44 editproperties=11 editundo=20
exitapp=44 highglightdefaultcolor=7 launchopentarget=2 launchprogramfpga=542
managecompositetargets=1 newhardwaredashboard=14 newproject=1 opendeviceview=3
openexistingreport=3 openhardwaremanager=47 openproject=7 openrecenttarget=13
programdevice=3 projectsummary=7 recustomizecore=34 refreshdevice=2
refreshserver=2 refreshtarget=1 reloaddesign=1 reportipstatus=3
reporttimingsummary=2 resetlayout=1 runbitgen=774 rundesignahead=1
runimplementation=53 runschematic=1 runsynthesis=24 savefileproxyhandler=13
saveprojectas=1 settopnode=6 showproductguide=5 showsource=3
showview=111 simulationbreak=3 simulationclose=1 simulationrelaunch=2
simulationrestart=1 simulationrun=38 simulationrunall=9 timingconstraintswizard=1
toolssettings=23 toolstemplates=1 unhighlightselection=10 unroute=1
unselectallcmdhandler=2 upgradeip=6 verifydevice=3 viewlayoutcmd=3
viewtaskimplementation=17 viewtaskprojectmanager=1 viewtasksynthesis=4 xdccreateclock=1
xdccreategeneratedclock=3 zoomfit=1 zoomin=14 zoomout=15
other_data
guimode=44
project_data
constraintsetcount=1 core_container=true currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=50 export_simulation_ies=50
export_simulation_modelsim=51 export_simulation_questa=50 export_simulation_riviera=50 export_simulation_vcs=50
export_simulation_xsim=51 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=42 simulator_language=Mixed srcsetcount=22 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=8 totalsynthesisruns=11

unisim_transformation
post_unisim_transformation
bufg=9 bufio=1 bufr=1 carry4=16
fdce=152 fdpe=6 fdre=426 fdse=14
gnd=25 ibuf=8 lut1=32 lut2=93
lut3=148 lut4=113 lut5=116 lut6=295
mmcme2_adv=1 muxf7=6 obuf=18 obufds=4
obuftds=4 oddr=16 oserdese2=7 plle2_adv=1
srl16e=2 vcc=29
pre_unisim_transformation
bufg=9 bufio=1 bufr=1 carry4=16
fdce=152 fdpe=6 fdre=426 fdse=14
gnd=25 ibuf=8 lut1=32 lut2=93
lut3=148 lut4=113 lut5=116 lut6=295
mmcme2_adv=1 muxf7=6 obuf=18 obufds=4
obuftds=4 oddr=16 oserdese2=7 plle2_adv=1
srl16e=2 vcc=29

ip_statistics
clk_wiz_v6_0_6_0_0/1
clkin1_period=37.037 clkin2_period=10.0 clock_mgr_type=NA component_name=clk27m25p2m
core_container=NA enable_axi=0 feedback_source=FDBK_ONCHIP feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=5 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
clk_wiz_v6_0_6_0_0/2
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=pll100m27m
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=true use_phase_alignment=true
use_power_down=false use_reset=true
selectio_wiz_v5_1_15/1
active_edge=RISING bus_dir=OUTPUTS bus_in_delay=NONE bus_io_std=TMDS_33
bus_out_delay=NONE bus_sig_type=DIFF clk_buf=BUFIO2 clk_delay=NONE
clk_io_std=LVCMOS18 clk_sig_type=SINGLE component_name=TMDS_TX core_container=true
ddr_alignment=C0 enable_bitslip=false enable_train=false interface_type=NETWORKING
iptotal=1 selio_active_edge=DDR selio_bus_in_delay=NONE selio_bus_in_tap=0
selio_bus_out_delay=NONE selio_bus_out_tap=0 selio_clk_buf=MMCM selio_clk_io_std=TMDS_33
selio_clk_sig_type=DIFF selio_ddr_alignment=SAME_EDGE_PIPELINED selio_interface_type=NETWORKING selio_oddr_alignment=SAME_EDGE
serialization_factor=10 system_data_width=3 use_phase_detector=false use_serialization=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.002880 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.072960
die=xc7s50csga324-1 dsp_output_toggle=12.500000 dynamic=0.577873 effective_thetaja=4.94
enable_probability=0.990000 family=spartan7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.353722 input_toggle=12.500000 junction_temp=28.2 (C)
logic=0.001412 mmcm=0.092346 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.650834 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=csga324 pct_clock_constrained=2.000000 pct_inputs_defined=12 platform=nt64
pll=0.126329 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.001184
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=7.6 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=4.94 user_junc_temp=28.2 (C) user_thetajb=7.6 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.118472 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.012697 vccaux_total_current=0.131169 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000000 vccbram_static_current=0.000178 vccbram_total_current=0.000178 vccbram_voltage=1.000000
vccint_dynamic_current=0.020088 vccint_static_current=0.010628 vccint_total_current=0.030716 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.104405 vcco33_static_current=0.001000 vcco33_total_current=0.105405 vcco33_voltage=3.300000
version=2020.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=4 bufgctrl_util_percentage=12.50
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_only_fixed=0 bufio_only_used=1
bufio_used=1 bufio_util_percentage=5.00 bufmrce_available=10 bufmrce_fixed=0
bufmrce_used=0 bufmrce_util_percentage=0.00 bufr_available=20 bufr_fixed=0
bufr_used=1 bufr_util_percentage=5.00 mmcme2_adv_available=5 mmcme2_adv_fixed=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00 plle2_adv_available=5 plle2_adv_fixed=0
plle2_adv_used=1 plle2_adv_util_percentage=20.00
dsp
dsps_available=120 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=1 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=75 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=150 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=75 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=4 bufio_functional_category=Clock bufio_used=1
bufr_functional_category=Clock bufr_used=1 carry4_functional_category=CarryLogic carry4_used=16
fdce_functional_category=Flop & Latch fdce_used=152 fdpe_functional_category=Flop & Latch fdpe_used=6
fdre_functional_category=Flop & Latch fdre_used=426 fdse_functional_category=Flop & Latch fdse_used=14
ibuf_functional_category=IO ibuf_used=8 lut1_functional_category=LUT lut1_used=30
lut2_functional_category=LUT lut2_used=93 lut3_functional_category=LUT lut3_used=148
lut4_functional_category=LUT lut4_used=113 lut5_functional_category=LUT lut5_used=116
lut6_functional_category=LUT lut6_used=295 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=6 obuf_functional_category=IO obuf_used=18
obufds_functional_category=IO obufds_used=4 obuftds_functional_category=IO obuftds_used=4
oddr_functional_category=IO oddr_used=12 oserdese2_functional_category=IO oserdese2_used=7
plle2_adv_functional_category=Clock plle2_adv_used=1 srl16e_functional_category=Distributed Memory srl16e_used=2
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=6 f7_muxes_util_percentage=0.04
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=32600 lut_as_logic_fixed=0
lut_as_logic_used=602 lut_as_logic_util_percentage=1.85 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=2 lut_as_memory_util_percentage=0.02 lut_as_shift_register_fixed=0 lut_as_shift_register_used=2
register_as_flip_flop_available=65200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=598 register_as_flip_flop_util_percentage=0.92
register_as_latch_available=65200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=32600 slice_luts_fixed=0 slice_luts_used=604 slice_luts_util_percentage=1.85
slice_registers_available=65200 slice_registers_fixed=0 slice_registers_used=598 slice_registers_util_percentage=0.92
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=32600 lut_as_logic_fixed=0
lut_as_logic_used=602 lut_as_logic_util_percentage=1.85 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=2 lut_as_memory_util_percentage=0.02 lut_as_shift_register_fixed=0 lut_as_shift_register_used=2
lut_in_front_of_the_register_is_unused_fixed=2 lut_in_front_of_the_register_is_unused_used=92 lut_in_front_of_the_register_is_used_fixed=92 lut_in_front_of_the_register_is_used_used=62
register_driven_from_outside_the_slice_fixed=62 register_driven_from_outside_the_slice_used=154 register_driven_from_within_the_slice_fixed=154 register_driven_from_within_the_slice_used=444
slice_available=8150 slice_fixed=0 slice_registers_available=65200 slice_registers_fixed=0
slice_registers_used=598 slice_registers_util_percentage=0.92 slice_used=216 slice_util_percentage=2.65
slicel_fixed=0 slicel_used=141 slicem_fixed=0 slicem_used=75
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=14 unique_control_sets_util_percentage=0.17
using_o5_and_o6_fixed=0.17 using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=2
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified] -max_bram=default::-1
-max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1
-mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7s50csga324-1 -resource_sharing=default::auto
-retiming=[specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified]
-seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3 -top=cq_dvitx3
-verilog_define=default::[not_specified]
usage
elapsed=00:00:31s hls_ip=0 memory_gain=16.910MB memory_peak=1018.246MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::