Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3064766
date_generatedTue Jun 22 13:46:38 2021 os_platformWIN64
product_versionVivado v2020.2 (64-bit) project_iddedbf15c49b04a93ae020a828de05853
project_iteration80 random_id4a563824606552e4a83491e92929bc30
registration_id211376274_0_0_851 route_designTRUE
target_devicexc7z010i target_familyzynq
target_packageclg400 target_speed-1L
tool_flowVivado

user_environment
cpu_nameAMD Ryzen 9 3900X 12-Core Processor cpu_speed3793 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram17.000 GB total_processors2

vivado_usage
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 addsrcwizard_specify_or_create_constraint_files=1 basedialog_cancel=14 basedialog_no=1
basedialog_ok=37 basedialog_yes=1 basereporttab_rerun=1 cmdmsgdialog_ok=10
confirmsavetexteditsdialog_no=1 constraintschooserpanel_add_files=1 coretreetablepanel_core_tree_table=9 customizecoredialog_documentation=1
filesetpanel_file_set_panel_tree=906 floatingtopdialog_ignore_and_continue_with_invalid_top=1 floatingtopdialog_select_top_module_of_your_design=1 floatingtopdialog_specify_new_top_module=1
flownavigatortreepanel_flow_navigator_tree=57 gettingstartedview_open_project=4 hardwaretreepanel_hardware_tree_table=22 hcodeeditor_search_text_combo_box=16
ipstatussectionpanel_upgrade_selected=1 ipstatustablepanel_ip_status_table=13 ipstatustablepanel_more_info=6 ipstatustablepanel_view_change_log=1
mainmenumgr_edit=24 mainmenumgr_file=12 mainmenumgr_flow=22 mainmenumgr_project=5
mainmenumgr_reports=16 mainmenumgr_settings=3 mainmenumgr_tools=18 mainmenumgr_view=2
mainmenumgr_window=18 mainwinmenumgr_layout=4 msgtreepanel_message_view_tree=53 msgview_clear_messages_resulting_from_user_executed=5
msgview_critical_warnings=15 msgview_error_messages=3 msgview_information_messages=5 msgview_status_messages=2
msgview_warning_messages=25 openfileaction_ok=3 pacommandnames_add_sources=6 pacommandnames_auto_connect_target=6
pacommandnames_auto_update_hier=14 pacommandnames_core_gen=2 pacommandnames_create_hardware_dashboards=1 pacommandnames_edit_constraint_sets=1
pacommandnames_fileset_window=2 pacommandnames_find_in_files=1 pacommandnames_goto_instantiation=1 pacommandnames_program_fpga=11
pacommandnames_recustomize_core=1 pacommandnames_report_ip_status=2 pacommandnames_run_bitgen=1 pacommandnames_show_product_guide=1
pacommandnames_simulation_run=2 paviews_code=22 paviews_ip_catalog=1 paviews_project_summary=2
programfpgadialog_program=9 programfpgadialog_specify_bitstream_file=1 progressdialog_cancel=2 rdicommands_custom_commands=1
rdicommands_delete=11 reportipstatusinfodialog_report_ip_status=1 saveprojectutils_cancel=1 saveprojectutils_save=1
srcchooserpanel_add_directories=4 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=6 srcchooserpanel_add_sources_from_subdirectories=1 srcfileproppanels_enabled=2
srcmenu_ip_documentation=6 srcmenu_ip_hierarchy=13 srcmenu_open_selected_source_files=1 syntheticagettingstartedview_recent_projects=1
syntheticastatemonitor_cancel=1 tclconsoleview_tcl_console_code_editor=1
java_command_handlers
addsources=24 archiveproject=2 autoconnecttarget=36 closeproject=1
closetarget=2 copyiphandler=10 coreview=14 createblockdesign=4
createhardwaredashboards=3 customizecore=10 editconstraintsets=1 editdelete=61
editpaste=23 editproperties=5 editundo=4 exitapp=2
generateoutputforbdfile=1 launchprogramfpga=108 managecompositetargets=2 newhardwaredashboard=6
newproject=1 openblockdesign=4 opencheckpoint=1 openexample=1
openhardwaremanager=57 openproject=5 openrecenttarget=28 openrsbhierarchyblock=1
opentarget=1 programdevice=26 projectsummary=1 recustomizecore=65
refreshdevice=2 refreshtarget=4 reportipstatus=3 runbitgen=140
runimplementation=32 runsynthesis=24 saveallfiles=1 savefileproxyhandler=11
setglobalinclude=1 setsourceenabled=4 settopnode=3 showproductguide=3
showproductwebpage=2 showsource=2 showview=63 toolssettings=15
toolstemplates=4 ui.views.c.h.f=1 upgradeip=1 verifydevice=1
viewlayoutcmd=2 viewtaskimplementation=4 viewtaskprojectmanager=1 viewtaskrtlanalysis=2
viewtasksynthesis=1
other_data
guimode=27
project_data
constraintsetcount=1 core_container=true currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=29 export_simulation_ies=29
export_simulation_modelsim=29 export_simulation_questa=29 export_simulation_riviera=29 export_simulation_vcs=29
export_simulation_xsim=29 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=12 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=5 totalsynthesisruns=5

unisim_transformation
post_unisim_transformation
bufg=3 bufio=1 bufr=1 carry4=50
fdce=75 fdre=541 gnd=16 ibuf=3
lut1=41 lut2=100 lut3=122 lut4=108
lut5=169 lut6=329 mmcme2_adv=1 muxf7=18
obuf=24 obufds=4 obuft=1 oserdese2=7
plle2_adv=1 ramb18e1=1 srl16e=10 vcc=13
pre_unisim_transformation
bufg=3 bufio=1 bufr=1 carry4=50
fdce=75 fdre=541 gnd=16 ibuf=3
lut1=41 lut2=100 lut3=122 lut4=108
lut5=169 lut6=329 mmcme2_adv=1 muxf7=18
obuf=24 obufds=4 obuft=1 oserdese2=7
plle2_adv=1 ramb18e1=1 srl16e=10 vcc=13

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=618 srls_augmented=0
srls_newly_gated=0 srls_total=10

ip_statistics
clk_wiz_v6_0_6_0_0/1
clkin1_period=37.037 clkin2_period=10.0 clock_mgr_type=NA component_name=clk27m25p2m
core_container=NA enable_axi=0 feedback_source=FDBK_ONCHIP feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=5 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
clk_wiz_v6_0_6_0_0/2
clkin1_period=8.000 clkin2_period=10.000 clock_mgr_type=NA component_name=pll125m27m
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=true use_phase_alignment=true
use_power_down=false use_reset=true
selectio_wiz_v5_1_15/1
active_edge=RISING bus_dir=OUTPUTS bus_in_delay=NONE bus_io_std=TMDS_33
bus_out_delay=NONE bus_sig_type=DIFF clk_buf=BUFIO2 clk_delay=NONE
clk_io_std=LVCMOS18 clk_sig_type=SINGLE component_name=TMDS_TX core_container=true
ddr_alignment=C0 enable_bitslip=false enable_train=false interface_type=NETWORKING
iptotal=1 selio_active_edge=DDR selio_bus_in_delay=NONE selio_bus_in_tap=0
selio_bus_out_delay=NONE selio_bus_out_tap=0 selio_clk_buf=MMCM selio_clk_io_std=TMDS_33
selio_clk_sig_type=DIFF selio_ddr_alignment=SAME_EDGE_PIPELINED selio_interface_type=NETWORKING selio_oddr_alignment=SAME_EDGE
serialization_factor=10 system_data_width=3 use_phase_detector=false use_serialization=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
rpbf-3=1 zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
hpdr-1=1 timing-17=8

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.000179 clocks=0.001205
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.082491 die=xc7z010iclg400-1L dsp_output_toggle=12.500000 dynamic=0.360495
effective_thetaja=11.53 enable_probability=0.990000 family=zynq ff_toggle=12.500000
flow_state=routed heatsink=none i/o=0.136634 input_toggle=12.500000
junction_temp=30.1 (C) logic=0.001160 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 mmcm=0.092315 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.442986 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=clg400 pct_clock_constrained=2.000000 pct_inputs_defined=33
platform=nt64 pll=0.128123 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.000880 simulation_file=None speedgrade=-1L static_prob=False
temp_grade=industrial thetajb=9.3 (C/W) thetasa=0.0 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=11.53 user_junc_temp=30.1 (C) user_thetajb=9.3 (C/W)
user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.018000 vccadc_total_current=0.018000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.115440 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.005280 vccaux_total_current=0.120719
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000014 vccbram_static_current=0.000165 vccbram_total_current=0.000179
vccbram_voltage=0.950000 vccint_dynamic_current=0.017918 vccint_static_current=0.002630 vccint_total_current=0.020548
vccint_voltage=0.950000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.041112 vcco33_static_current=0.001000 vcco33_total_current=0.042112
vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000 vcco_ddr_total_current=0.000000
vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000
vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000
vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.009297 vccpaux_total_current=0.009297
vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.013037 vccpint_total_current=0.013037
vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.002700 vccpll_total_current=0.002700
vccpll_voltage=1.800000 version=2020.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=8 bufio_fixed=0 bufio_only_fixed=0 bufio_only_used=1
bufio_used=1 bufio_util_percentage=12.50 bufmrce_available=4 bufmrce_fixed=0
bufmrce_used=0 bufmrce_util_percentage=0.00 bufr_available=8 bufr_fixed=0
bufr_used=1 bufr_util_percentage=12.50 mmcme2_adv_available=2 mmcme2_adv_fixed=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=50.00 plle2_adv_available=2 plle2_adv_fixed=0
plle2_adv_used=1 plle2_adv_util_percentage=50.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=1
memory
block_ram_tile_available=60 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=0.83
ramb18_available=120 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=0.83
ramb18e1_only_used=1 ramb36_fifo_available=60 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 bufio_functional_category=Clock bufio_used=1
bufr_functional_category=Clock bufr_used=1 carry4_functional_category=CarryLogic carry4_used=50
fdce_functional_category=Flop & Latch fdce_used=75 fdre_functional_category=Flop & Latch fdre_used=543
ibuf_functional_category=IO ibuf_used=3 lut1_functional_category=LUT lut1_used=37
lut2_functional_category=LUT lut2_used=100 lut3_functional_category=LUT lut3_used=122
lut4_functional_category=LUT lut4_used=108 lut5_functional_category=LUT lut5_used=169
lut6_functional_category=LUT lut6_used=329 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=18 obuf_functional_category=IO obuf_used=24
obufds_functional_category=IO obufds_used=4 obuft_functional_category=IO obuft_used=1
oserdese2_functional_category=IO oserdese2_used=7 plle2_adv_functional_category=Clock plle2_adv_used=1
ramb18e1_functional_category=Block Memory ramb18e1_used=1 srl16e_functional_category=Distributed Memory srl16e_used=10
slice_logic
f7_muxes_available=8800 f7_muxes_fixed=0 f7_muxes_used=18 f7_muxes_util_percentage=0.20
f8_muxes_available=4400 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=17600 lut_as_logic_fixed=0
lut_as_logic_used=702 lut_as_logic_util_percentage=3.99 lut_as_memory_available=6000 lut_as_memory_fixed=0
lut_as_memory_used=10 lut_as_memory_util_percentage=0.17 lut_as_shift_register_fixed=0 lut_as_shift_register_used=10
register_as_flip_flop_available=35200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=618 register_as_flip_flop_util_percentage=1.76
register_as_latch_available=35200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=17600 slice_luts_fixed=0 slice_luts_used=712 slice_luts_util_percentage=4.05
slice_registers_available=35200 slice_registers_fixed=0 slice_registers_used=618 slice_registers_util_percentage=1.76
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=17600 lut_as_logic_fixed=0
lut_as_logic_used=702 lut_as_logic_util_percentage=3.99 lut_as_memory_available=6000 lut_as_memory_fixed=0
lut_as_memory_used=10 lut_as_memory_util_percentage=0.17 lut_as_shift_register_fixed=0 lut_as_shift_register_used=10
lut_in_front_of_the_register_is_unused_fixed=10 lut_in_front_of_the_register_is_unused_used=72 lut_in_front_of_the_register_is_used_fixed=72 lut_in_front_of_the_register_is_used_used=132
register_driven_from_outside_the_slice_fixed=132 register_driven_from_outside_the_slice_used=204 register_driven_from_within_the_slice_fixed=204 register_driven_from_within_the_slice_used=414
slice_available=4400 slice_fixed=0 slice_registers_available=35200 slice_registers_fixed=0
slice_registers_used=618 slice_registers_util_percentage=1.76 slice_used=255 slice_util_percentage=5.80
slicel_fixed=0 slicel_used=166 slicem_fixed=0 slicem_used=89
unique_control_sets_available=4400 unique_control_sets_fixed=4400 unique_control_sets_used=29 unique_control_sets_util_percentage=0.66
using_o5_and_o6_fixed=0.66 using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=2
using_o6_output_only_fixed=2 using_o6_output_only_used=8
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified] -max_bram=default::-1
-max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1
-mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7z010iclg400-1L -resource_sharing=default::auto
-retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified]
-seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3 -top=hdmiaudio_zybo
-verilog_define=default::[not_specified]
usage
elapsed=00:00:32s hls_ip=0 memory_gain=20.848MB memory_peak=1021.027MB